/*
 * Copyright 2019-2020 NXP
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
#ifndef _S32G_PINCTRL_H_
#define _S32G_PINCTRL_H_

#include "platform_def.h"

#define SIUL2_0_MSCR_BASE	(SIUL2_0_BASE_ADDR + 0x00000240)
#define SIUL2_0_IMCR_BASE	(SIUL2_0_BASE_ADDR + 0x00000A40)
#define SIUL2_1_MSCR_BASE	(SIUL2_1_BASE_ADDR + 0x00000400)
#define SIUL2_1_IMCR_BASE	(SIUL2_1_BASE_ADDR + 0x00000C1C)

/* MSCR 0-101 */
#define SIUL2_0_MSCRn(i)	(SIUL2_0_MSCR_BASE + 4 * (i))
/* MSCR 112-190 */
#define SIUL2_1_MSCRn(i)	(SIUL2_1_MSCR_BASE + 4 * (i - 112))
/* IMCR 0-83 */
#define SIUL2_0_IMCRn(i)	(SIUL2_0_IMCR_BASE +  4 * (i))
/* IMCR 119-495 */
#define SIUL2_1_IMCRn(i)	(SIUL2_1_IMCR_BASE +  4 * (i - 119))

#define SIUL2_MSCR_S32_G1_SRC_100MHz            (5 << 14)
#define SIUL2_MSCR_S32_G1_ODE_EN		BIT(20)
#define SIUL2_MSCR_S32_G1_OBE_EN		BIT(21)
#define SIUL2_MSCR_S32_G1_IBE_EN		BIT(19)
#define SIUL2_MSCR_S32_G1_PUE_EN		BIT(13)
#define SIUL2_MSCR_S32_G1_PUS_EN		BIT(12)
#define SIUL2_MSCR_S32_G1_SMC_DIS		BIT(5)
#define SIUL2_MSCR_MUX_MODE_ALT0		(0x0)
#define SIUL2_MSCR_MUX_MODE_ALT1		(0x1)
#define SIUL2_MSCR_MUX_MODE_ALT2		(0x2)
#define SIUL2_MSCR_MUX_MODE_ALT3		(0x3)
#define SIUL2_MSCR_MUX_MODE_ALT4		(0x4)
#define SIUL2_MSCR_MUX_MODE_ALT5		(0x5)

/*
 * Pinctrl for LinFlexD-UART
 */
#define SIUL2_MSCR_S32G_G1_PORT_CTRL_UART0_TXD	\
	(SIUL2_MSCR_S32_G1_SRC_100MHz |		\
	 SIUL2_MSCR_S32_G1_OBE_EN |		\
	 SIUL2_MSCR_MUX_MODE_ALT1)

#define SIUL2_MSCR_S32G_G1_PORT_CTRL_UART_RXD	\
	(SIUL2_MSCR_S32_G1_SRC_100MHz |		\
	 SIUL2_MSCR_S32_G1_IBE_EN |		\
	 SIUL2_MSCR_MUX_MODE_ALT0)

#define SIUL2_IMCR_S32G_G1_UART0_RXD_to_pad	\
	(SIUL2_MSCR_MUX_MODE_ALT2)

#define SIUL2_PC09_MSCR_S32_G1_UART0		41
#define SIUL2_PC10_MSCR_S32_G1_UART0		42
#define SIUL2_PC10_IMCR_S32_G1_UART0		(512 - 512)

/*
 * Pinctrl for SDHC
 */
#define SIUL2_MSCR_S32_G1_SRC_208MHz		(0 << 14)
#define SIUL2_USDHC_S32_G1_PAD_CTRL_BASE \
	(SIUL2_MSCR_S32_G1_SRC_208MHz | \
	 SIUL2_MSCR_S32_G1_OBE_EN | \
	 SIUL2_MSCR_S32_G1_IBE_EN | \
	 SIUL2_MSCR_S32_G1_PUE_EN | \
	 SIUL2_MSCR_S32_G1_SMC_DIS)
#define SIUL2_USDHC_S32_G1_PAD_CTRL_CLK \
	(SIUL2_USDHC_S32_G1_PAD_CTRL_BASE | \
	 SIUL2_MSCR_MUX_MODE_ALT1)
#define SIUL2_USDHC_S32_G1_PAD_CTRL_CMD \
	(SIUL2_USDHC_S32_G1_PAD_CTRL_BASE | \
	 SIUL2_MSCR_S32_G1_PUS_EN | \
	 SIUL2_MSCR_MUX_MODE_ALT1)
#define SIUL2_USDHC_S32_G1_PAD_CTRL_DATA \
	(SIUL2_USDHC_S32_G1_PAD_CTRL_BASE | \
	 SIUL2_MSCR_S32_G1_PUS_EN | \
	 SIUL2_MSCR_MUX_MODE_ALT1)
#define SIUL2_USDHC_S32_G1_PAD_RST \
	(SIUL2_MSCR_S32_G1_SRC_208MHz | \
	 SIUL2_MSCR_S32_G1_OBE_EN | \
	 SIUL2_MSCR_S32_G1_PUE_EN | \
	 SIUL2_MSCR_S32_G1_SMC_DIS | \
	 SIUL2_MSCR_MUX_MODE_ALT1)

/*
 * Pinctrl for I2C
 */
#define SIUL2_MSCR_S32G_PB_00   16
#define SIUL2_MSCR_S32G_PB_01   17
#define SIUL2_MSCR_S32G_PB_03   19
#define SIUL2_MSCR_S32G_PB_04   20
#define SIUL2_MSCR_S32G_PB_05   21
#define SIUL2_MSCR_S32G_PB_06   22
#define SIUL2_MSCR_S32G_PB_07   23
#define SIUL2_MSCR_S32G_PB_13   29
#define SIUL2_MSCR_S32G_PB_15   31
#define SIUL2_MSCR_S32G_PC_00   32
#define SIUL2_MSCR_S32G_PC_01   33
#define SIUL2_MSCR_S32G_PC_02   34
#define SIUL2_MSCR_S32G_PK_03   163
#define SIUL2_MSCR_S32G_PK_05   165
#define SIUL2_PB_00_IMCR_S32G_I2C0_SDA  (565 - 512)
#define SIUL2_PB_01_IMCR_S32G_I2C0_SCLK (566 - 512)
#define SIUL2_PB_03_IMCR_S32G_I2C1_SCLK (717 - 512)
#define SIUL2_PB_04_IMCR_S32G_I2C1_SDA  (718 - 512)
#define SIUL2_PK_03_IMCR_S32G_I2C1_SCLK (717 - 512)
#define SIUL2_PK_05_IMCR_S32G_I2C1_SDA  (718 - 512)
#define SIUL2_PB_05_IMCR_S32G_I2C2_SCLK (719 - 512)
#define SIUL2_PB_06_IMCR_S32G_I2C2_SDA  (720 - 512)
#define SIUL2_PB_07_IMCR_S32G_I2C3_SCLK (721 - 512)
#define SIUL2_PB_13_IMCR_S32G_I2C3_SDA  (722 - 512)
#define SIUL2_PC_01_IMCR_S32G_I2C4_SDA  (724 - 512)
#define SIUL2_PC_02_IMCR_S32G_I2C4_SCLK (723 - 512)
#define SIUL2_PB_15_IMCR_S32G_I2C1_SDA  (565 - 512)
#define SIUL2_PC_00_IMCR_S32G_I2C1_SCLK (566 - 512)

#define SIUL2_MSCR_S32G_I2C_SDA \
	(SIUL2_MSCR_S32_G1_OBE_EN | \
	 SIUL2_MSCR_S32_G1_IBE_EN | \
	 SIUL2_MSCR_S32_G1_ODE_EN)

#define SIUL2_MSCR_S32G_I2C_SCLK \
	(SIUL2_MSCR_S32_G1_OBE_EN | \
	 SIUL2_MSCR_S32_G1_IBE_EN | \
	 SIUL2_MSCR_S32_G1_ODE_EN)

/* I2C0 - Serial Data Input */
#define SIUL2_MSCR_S32G_PAD_CTRL_I2C0_SDA \
	(SIUL2_MSCR_MUX_MODE_ALT1 | \
	 SIUL2_MSCR_S32G_I2C_SDA)
#define SIUL2_MSCR_S32G_PAD_CTRL_I2C0_SDA_ALT2 \
	(SIUL2_MSCR_MUX_MODE_ALT2 | \
	 SIUL2_MSCR_S32G_I2C_SDA)
#define SIUL2_IMCR_S32G_PAD_CTRL_I2C0_SDA (SIUL2_MSCR_MUX_MODE_ALT2)
#define SIUL2_IMCR_S32G_PAD_CTRL_I2C0_SDA_ALT3 (SIUL2_MSCR_MUX_MODE_ALT3)

/* I2C0 - Serial Clock Input */
#define SIUL2_MSCR_S32G_PAD_CTRL_I2C0_SCLK \
	(SIUL2_MSCR_MUX_MODE_ALT1 | \
	 SIUL2_MSCR_S32G_I2C_SCLK)
#define SIUL2_IMCR_S32G_PAD_CTRL_I2C0_SCLK (SIUL2_MSCR_MUX_MODE_ALT2)
#define SIUL2_IMCR_S32G_PAD_CTRL_I2C0_SCLK_ALT3 (SIUL2_MSCR_MUX_MODE_ALT3)

/* I2C1 - Serial Data Input */
#define SIUL2_MSCR_S32G_PAD_CTRL_I2C1_SDA \
	(SIUL2_MSCR_MUX_MODE_ALT1 | \
	 SIUL2_MSCR_S32G_I2C_SDA)

#define SIUL2_MSCR_S32G_PAD_CTRL_I2C1_SDA_ALT3 \
	(SIUL2_MSCR_MUX_MODE_ALT3 | \
	 SIUL2_MSCR_S32G_I2C_SDA)
#define SIUL2_IMCR_S32G_PAD_CTRL_I2C1_SDA (SIUL2_MSCR_MUX_MODE_ALT2)
#define SIUL2_IMCR_S32G_PAD_CTRL_I2C1_SDA_ALT4 (SIUL2_MSCR_MUX_MODE_ALT4)

/* I2C1 - Serial Clock Input */
#define SIUL2_MSCR_S32G_PAD_CTRL_I2C1_SCLK \
	(SIUL2_MSCR_MUX_MODE_ALT1 | \
	 SIUL2_MSCR_S32G_I2C_SCLK)

#define SIUL2_MSCR_S32G_PAD_CTRL_I2C1_SCLK_ALT3 \
	(SIUL2_MSCR_MUX_MODE_ALT3 | \
	 SIUL2_MSCR_S32G_I2C_SCLK)
#define SIUL2_IMCR_S32G_PAD_CTRL_I2C1_SCLK (SIUL2_MSCR_MUX_MODE_ALT2)
#define SIUL2_IMCR_S32G_PAD_CTRL_I2C1_SCLK_ALT5 (SIUL2_MSCR_MUX_MODE_ALT5)

/* I2C2 - Serial Data Input */
#define SIUL2_MSCR_S32G_PAD_CTRL_I2C2_SDA \
	(SIUL2_MSCR_MUX_MODE_ALT1 | \
	 SIUL2_MSCR_S32G_I2C_SDA)
#define SIUL2_IMCR_S32G_PAD_CTRL_I2C2_SDA (SIUL2_MSCR_MUX_MODE_ALT2)

/* I2C2 - Serial Clock Input */
#define SIUL2_MSCR_S32G_PAD_CTRL_I2C2_SCLK \
	(SIUL2_MSCR_MUX_MODE_ALT1 | \
	 SIUL2_MSCR_S32G_I2C_SCLK)
#define SIUL2_IMCR_S32G_PAD_CTRL_I2C2_SCLK (SIUL2_MSCR_MUX_MODE_ALT2)

/* I2C3 - Serial Data Input */
#define SIUL2_MSCR_S32G_PAD_CTRL_I2C3_SDA \
	(SIUL2_MSCR_MUX_MODE_ALT2 | \
	 SIUL2_MSCR_S32G_I2C_SDA)
#define SIUL2_IMCR_S32G_PAD_CTRL_I2C3_SDA (SIUL2_MSCR_MUX_MODE_ALT4)

/* I2C3 - Serial Clock Input */
#define SIUL2_MSCR_S32G_PAD_CTRL_I2C3_SCLK \
	(SIUL2_MSCR_MUX_MODE_ALT1 | \
	 SIUL2_MSCR_S32G_I2C_SCLK)
#define SIUL2_IMCR_S32G_PAD_CTRL_I2C3_SCLK (SIUL2_MSCR_MUX_MODE_ALT2)

/* I2C4 - Serial Data Input */
#define SIUL2_MSCR_S32G_PAD_CTRL_I2C4_SDA \
	(SIUL2_MSCR_MUX_MODE_ALT1 | \
	 SIUL2_MSCR_S32G_I2C_SDA)
#define SIUL2_IMCR_S32G_PAD_CTRL_I2C4_SDA (SIUL2_MSCR_MUX_MODE_ALT3)

/* I2C4 - Serial Clock Input */
#define SIUL2_MSCR_S32G_PAD_CTRL_I2C4_SCLK \
	(SIUL2_MSCR_MUX_MODE_ALT2 | \
	 SIUL2_MSCR_S32G_I2C_SCLK)
#define SIUL2_IMCR_S32G_PAD_CTRL_I2C4_SCLK (SIUL2_MSCR_MUX_MODE_ALT3)

void s32g_plat_config_pinctrl(void);
void i2c_config_pinctrl(void);

#endif
